This application claims priority from Korean Patent Application No. 2002-51194, filed Aug. 28, 2002, which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to masks for manufacturing a highly-integrated circuit device, a method of creating a layout of the mask, a method of manufacturing the mask and a method of manufacturing the highly-integrated circuit device using the mask.
2. Description of the Related Art
As the integration density of semiconductor devices increases, design rules are scaled down into the deep submicron range and under. However, the smaller the size of the pattern, the less resolution the pattern has due to optical proximity effects between adjacent patterns.
If the numerical aperture is increased to increase the resolution of an optical apparatus, the depth of focus (DOF) is undesirably decreased. Thus, a phase shift mask (PSM) for shifting and interfering with a wavelength of light transmitted through the mask has been introduced to improve the resolution.
U.S. Pat. No. 5,858,580 discloses a mask that minimizes a gate line width of a transistor using the characteristics of a PSM. In this reference, the PSM defines the gate on an active area and a single phase structure mask (SPSM) defines remaining interconnection structures. A semiconductor substrate is exposed using PSM and the SPSM (double-exposed) so that the gate line width on the active area can be reduced compared to a prior art method.
In the set of masks disclosed in U.S. Pat. No. 5,858,580, however, only a single straight line type gate pattern is defined on the active area by the PSM, while the remaining interconnection structures are defined by a chrome pattern of the SPSM. Thus, with the prior art method described above using the PSM and the SPSM masks, the gate line width on the active area can be reduced compared to the conventional gate line width. But the line width of the remaining interconnection structures connecting the remaining gates has not been reduced as desired. Therefore, it is difficult to form the highly-integrated device on a small chip area using the prior art techniques.